https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9133073 [ieee.org] Here we briefly explain the basics of SubRISC+ to the extent of highlighting our contributions in this paper. SubRISC+ was developed on the basis of a one-instruction set computer (OISC) whose unique instruction is ‘‘subtraction and branch on negative’’ that is capable of realizing any operations and hence is Turing complete. By extending the instruction set architecture (ISA) of this OISC, SubRISC+ handles four instructions (subtraction, bitwise AND, shift, and memory access) that can be flexibly expressed in either 16 bits (for compactness) or 32 bits (to support an immediate value or branch) to improve computing and power efficiency while retaining simplicity with a very limited circuit overhead.
bne a0, t1, .L2 → sub a0, t1, t3, .L2 (two 32-bit instructios) sub t1, a0, t3, .L2
not a0, a1 → sub -1, a1, a0 (one 16-bit instruction)
subtract and branch if less than(sublt)命令です。subleqではありません。
減算+ブランチ命令、AND命令、シフト命令、メモリアクセス命令の四つ (スコア:0)
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9133073 [ieee.org]
Here we briefly explain the basics of SubRISC+ to the extent of highlighting our contributions in this paper.
SubRISC+ was developed on the basis of a one-instruction set computer (OISC) whose unique instruction is ‘‘subtraction and branch on negative’’ that is capable of realizing any operations and hence is Turing complete.
By extending the instruction set architecture (ISA) of this OISC, SubRISC+ handles four instructions (subtraction, bitwise AND, shift, and memory access) that can be flexibly expressed in either 16 bits (for compactness) or 32 bits (to support an immediate value or branch) to improve computing and power efficiency while retaining simplicity with a very limited circuit overhead.
bne a0, t1, .L2 →
sub a0, t1, t3, .L2 (two 32-bit instructios)
sub t1, a0, t3, .L2
not a0, a1 →
sub -1, a1, a0 (one 16-bit instruction)
subtract and branch if less than(sublt)命令です。subleqではありません。